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Figure 19.1. TIMER Block Overview
HFPERCLK TIMERn
Prescaler
CNTCLK
Counter
Note: For sim plicity, all
Quadrature
Decoder
control
TIMERn_CNT
Input Capture
Update
condition
TIMERn_TOP
=
= 0
TIMERn_CCx registers are
grouped together in the figure,
but they all have individual Input
Capture Registers
Overflow
Underflow
TIMn_CC0
PRS inputs
Input logic
Edge
detect
Com pare Match x
==
TIMn_CC1
PRS inputs
TIMn_CC2
PRS inputs
Input logic
Input logic
Edge
detect
Edge
detect
TnCCR1[ 15:0
TIMERn_CCx
TnCCR0[ 15:0
]
]
=
Com pare and
PWM config
Com pare and
PWM config
Com pare and
PWM config
TIMn_CC0
TIMn_CC1
TIMn_CC2
19.3.1 Counter Modes
The Timer consists of a counter that can be configured to the following modes:
1. Up-count: Counter counts up until it reaches the value in TIMERn_TOP, where it is reset to 0 before
counting up again.
2. Down-count: The counter starts at the value in TIMERn_TOP and counts down. When it reaches 0,
it is reloaded with the value in TIMERn_TOP.
3. Up/Down-count: The counter starts at 0 and counts up. When it reaches the value in TIMERn_TOP,
it counts down until it reaches 0 and starts counting up again.
4. Quadrature Decoder: Two input channels where one determines the count direction, while the other
pin triggers a clock event.
The counter value can be read or written by software at any time by accessing the CNT field in
TIMERn_CNT.
19.3.1.1 Events
Overflow is set when the counter value shifts from TIMERn_TOP to the next value when counting up. In
up-count mode the next value is 0. In up/down-count mode, the next value is TIMERn_TOP-1.
Underflow is set when the counter value shifts from 0 to the next value when counting down. In down-
count mode, the next value is TIMERn_TOP. In up/down-count mode the next value is 1.
Update event is set on overflow in up-count mode and on underflow in down-count or up/down count
mode. This event is used to time updates of buffered values.
19.3.1.2 Operation
Figure 19.2 (p. 247) shows the hardware Timer/Counter control. Software can start or stop the counter
by writing a 1 to the START or STOP bits in TIMERn_CMD. The counter value (CNT in TIMERn_CNT)
can always be written by software to any 16-bit value.
It is also possible to control the counter through either an external pin or PRS input. This is done through
the input logic for the Compare/Capture Channel 0. The Timer/Counter allows individual actions (start,
stop, reload) to be taken for rising and falling input edges. This is configured in the RISEA and FALLA
2011-04-12 - d0001_Rev1.10
246
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